[MLton-commit] r7430
Matthew Fluet
fluet at mlton.org
Fri Feb 19 06:35:23 PST 2010
Fix register allocation spilling bug.
With PIC on x86-linux, %ebx is reserved for the GOT; this eliminates
the only byte-sized callee save register, which caused the spilling
bug when trying to shuffle registers across a C call.
----------------------------------------------------------------------
U mlton/trunk/mlton/codegen/amd64-codegen/amd64-allocate-registers.fun
U mlton/trunk/mlton/codegen/x86-codegen/x86-allocate-registers.fun
----------------------------------------------------------------------
Modified: mlton/trunk/mlton/codegen/amd64-codegen/amd64-allocate-registers.fun
===================================================================
--- mlton/trunk/mlton/codegen/amd64-codegen/amd64-allocate-registers.fun 2010-02-19 14:35:11 UTC (rev 7429)
+++ mlton/trunk/mlton/codegen/amd64-codegen/amd64-allocate-registers.fun 2010-02-19 14:35:13 UTC (rev 7430)
@@ -1,4 +1,5 @@
-(* Copyright (C) 1999-2007 Henry Cejtin, Matthew Fluet, Suresh
+(* Copyright (C) 1999-2010 Matthew Fluet.
+ * Copyright (C) 1999-2007 Henry Cejtin, Matthew Fluet, Suresh
* Jagannathan, and Stephen Weeks.
* Copyright (C) 1997-2000 NEC Research Institute.
*
@@ -5994,6 +5995,15 @@
registerAllocation = registerAllocation}
end)
+ val availCalleeSaveXmmRegisters =
+ List.keepAll
+ (XmmRegister.calleeSaveRegisters,
+ fn calleeSaveReg =>
+ List.forall
+ (#xmmreserved registerAllocation,
+ fn reservedReg =>
+ not (XmmRegister.coincide (reservedReg, calleeSaveReg))))
+
val {assembly = assembly_xmmshuffle,
registerAllocation, ...}
= if !Control.Native.shuffle then
@@ -6006,12 +6016,17 @@
andalso
(not o ClassSet.contains)
(cargClasses,
- MemLoc.class memloc)),
+ MemLoc.class memloc))
+ andalso
+ List.exists
+ (availCalleeSaveXmmRegisters,
+ fn calleeSaveReg =>
+ Size.eq (XmmRegister.size register,
+ XmmRegister.size calleeSaveReg)),
registerAllocation = registerAllocation},
{assembly = AppendList.empty,
- registerAllocation = registerAllocation,
- saves = []},
- fn ({memloc, ...}, {assembly, registerAllocation, saves})
+ registerAllocation = registerAllocation},
+ fn ({memloc, ...}, {assembly, registerAllocation})
=> let
val {assembly = assembly_shuffle,
registerAllocation, ...}
@@ -6022,20 +6037,27 @@
size = MemLoc.size memloc,
move = true,
supports = [],
- saves = saves,
+ saves = [],
force = XmmRegister.calleeSaveRegisters,
registerAllocation
= registerAllocation}
in
{assembly = AppendList.append (assembly,
assembly_shuffle),
- registerAllocation = registerAllocation,
- saves = saves}
+ registerAllocation = registerAllocation}
end)
else {assembly = AppendList.empty,
- registerAllocation = registerAllocation,
- saves = []}
+ registerAllocation = registerAllocation}
+ val availCalleeSaveRegisters =
+ List.keepAll
+ (Register.calleeSaveRegisters,
+ fn calleeSaveReg =>
+ List.forall
+ (#reserved registerAllocation,
+ fn reservedReg =>
+ not (Register.coincide (reservedReg, calleeSaveReg))))
+
val {assembly = assembly_shuffle,
registerAllocation, ...}
= if !Control.Native.shuffle then
@@ -6048,12 +6070,17 @@
andalso
(not o ClassSet.contains)
(cargClasses,
- MemLoc.class memloc)),
+ MemLoc.class memloc))
+ andalso
+ List.exists
+ (availCalleeSaveRegisters,
+ fn calleeSaveReg =>
+ Size.eq (Register.size register,
+ Register.size calleeSaveReg)),
registerAllocation = registerAllocation},
{assembly = AppendList.empty,
- registerAllocation = registerAllocation,
- saves = []},
- fn ({memloc, ...}, {assembly, registerAllocation, saves})
+ registerAllocation = registerAllocation},
+ fn ({memloc, ...}, {assembly, registerAllocation})
=> let
val {assembly = assembly_shuffle,
registerAllocation, ...}
@@ -6066,19 +6093,17 @@
size = MemLoc.size memloc,
move = true,
supports = [],
- saves = saves,
+ saves = [],
force = Register.calleeSaveRegisters,
registerAllocation
= registerAllocation}
in
{assembly = AppendList.append (assembly,
assembly_shuffle),
- registerAllocation = registerAllocation,
- saves = saves}
+ registerAllocation = registerAllocation}
end)
else {assembly = AppendList.empty,
- registerAllocation = registerAllocation,
- saves = []}
+ registerAllocation = registerAllocation}
val registerAllocation
= xmmvalueMap {map = fn value as {register,
Modified: mlton/trunk/mlton/codegen/x86-codegen/x86-allocate-registers.fun
===================================================================
--- mlton/trunk/mlton/codegen/x86-codegen/x86-allocate-registers.fun 2010-02-19 14:35:11 UTC (rev 7429)
+++ mlton/trunk/mlton/codegen/x86-codegen/x86-allocate-registers.fun 2010-02-19 14:35:13 UTC (rev 7430)
@@ -1,4 +1,5 @@
-(* Copyright (C) 1999-2007 Henry Cejtin, Matthew Fluet, Suresh
+(* Copyright (C) 2010 Matthew Fluet.
+ * Copyright (C) 1999-2007 Henry Cejtin, Matthew Fluet, Suresh
* Jagannathan, and Stephen Weeks.
* Copyright (C) 1997-2000 NEC Research Institute.
*
@@ -5864,6 +5865,15 @@
registerAllocation = registerAllocation}
end)
+ val availCalleeSaveRegisters =
+ List.keepAll
+ (Register.calleeSaveRegisters,
+ fn calleeSaveReg =>
+ List.forall
+ (#reserved registerAllocation,
+ fn reservedReg =>
+ not (Register.coincide (reservedReg, calleeSaveReg))))
+
val {assembly = assembly_shuffle,
registerAllocation, ...}
= if !Control.Native.shuffle then
@@ -5872,12 +5882,17 @@
=> List.contains
(Register.callerSaveRegisters,
register,
- Register.eq),
+ Register.eq)
+ andalso
+ List.exists
+ (availCalleeSaveRegisters,
+ fn calleeSaveReg =>
+ Size.eq (Register.size register,
+ Register.size calleeSaveReg)),
registerAllocation = registerAllocation},
{assembly = AppendList.empty,
- registerAllocation = registerAllocation,
- saves = []},
- fn ({memloc, ...}, {assembly, registerAllocation, saves})
+ registerAllocation = registerAllocation},
+ fn ({memloc, ...}, {assembly, registerAllocation})
=> let
val {assembly = assembly_shuffle,
registerAllocation, ...}
@@ -5890,19 +5905,17 @@
size = MemLoc.size memloc,
move = true,
supports = [],
- saves = saves,
+ saves = [],
force = Register.calleeSaveRegisters,
registerAllocation
= registerAllocation}
in
{assembly = AppendList.append (assembly,
assembly_shuffle),
- registerAllocation = registerAllocation,
- saves = saves}
+ registerAllocation = registerAllocation}
end)
else {assembly = AppendList.empty,
- registerAllocation = registerAllocation,
- saves = []}
+ registerAllocation = registerAllocation}
val registerAllocation
= valueMap {map = fn value as {register,
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