x86 self-compile

Suresh Jagannathan suresh@research.nj.nec.com
Wed, 2 Aug 2000 17:59:56 -0400

   From: "Stephen Weeks" <sweeks@intertrust.com>
   Content-Type: text/plain; charset=us-ascii
   Date: Wed, 2 Aug 2000 11:50:06 -0700 (PDT)
   Reply-to: MLton@sourcelight.com
   X-UIDL: 2bc9bbb357d7ab836a46b48025d03bd9

   > Any idea on where the performance bottlenecks are?

   We're hoping liveness info will be a big win.  I've added stuff to propagate the 
   liveness info that was already being computed on CPS all the way down to the
   backend, but Matthew hasn't yet integrated it.  Stay tuned.

I'm surprised you think the performance hit is coming from register
allocation (as I presume better liveness analysis is only going
to benefit allocation).  I'd have thought that instruction selection
and general code-generation issues would have dominated.  Have you
guys had a chance to look at the assembly output to eyeball 
code-generation/instruction selection quality?

			    -- sj